TRACS-TRansient Activity Checking with Scan Cells

Inside digital systems, errors are a result of temporary and permanent faults, these last requiring less redundancy usually to be detected. Beyond traditional techniques as duplex with comparison or Self-Checking designs, one recently presented, and relevant in this context, is named Concurrent Scan Test (CST) [1]. CST enhances the IEEE 1149.1 (BST) infrastructure to detect faults concurrently, adding to every relevant scan cell the ability to compare node signals to the content of its internal flip-flop and synchronizing itself to the mission circuit upon a match. Temporary faults are mostly caused by power supply and electromagnetic noise, radiation (a growing concern as geometry shrinks) and physical degradation [2], a first step for permanent faults as IDDQ and Thermal monitoring supporters claim. Pointed as responsible for 90-99% of the errors, they are detectable with traditional techniques but the overhead impacts the reliability, mainly in a single VLSI chip. However, the hardware being not injured by these faults, many applications allow to reduce physical redundancy, a feature essential in new ICs.